Conventionally, embedded self-test circuit architecture is adopted for testing memory units, wherein a large quantity of control signal lines and data bus lines are used for transmitting signals, issuing instructions or performing operations. Although the aforementioned parallel architecture can achieve the effect of sending out an access instruction in every clock cycle to perform an full-speed test to the memory units. If the quantity of testing memory units becomes larger, the control signal lines and the data bus lines will increase the wiring area greatly during a chip design process, and the increased wiring area will incur a higher cost, particularly for the advanced manufacturing process <65 nm, having a more significant increase of the wiring area and incurring a much higher cost.
To overcome the aforementioned problems, some manufacturers adopt the serial method to solve the increased wiring area problem and lower the cost. For example, a serial standard such as IEEE 1149.1 or IEEE 1500 is adopted. Although the wiring area can be reduced, the serial method requires executing several instructions in a time period, while the parallel method only requires executing one instruction to complete the transmission of instructions or data, so that the testing time will be increased significantly. In other words, the time and cost are increased, and such increase makes the self-test circuit unable to support the full-speed test function which is an important test for testing the fault coverage of the memory units. If only the serial method is used for the testing, the issue of the wiring cost can be solved, but the memory units cannot be tested effectively.